Field of the Invention
The present invention relates to technology that, when executing a multi-thread program on a multi-core processor, dynamically changes the allocation of operation cores to threads of the program.
Description of the Related Art
In recent years, processors in which a plurality of cores (parts that perform operation processing) are provided have become mainstream. Processors configured in such a manner are called “multi-core processors”, and a plurality of threads (execution units of processing) can be simultaneously executed by the respective processor cores. Multi-core processors are not only configured to be mounted in desktop PCs and server apparatuses but also to be mounted in embedded devices such as image forming apparatuses. In the case where a multi-core processor is mounted in an image forming apparatus, a configuration is often used in which a cache is provided for each core and a RAM is shared. In the case of such a configuration, cache misses may frequently occur depending on the running program, due to processing for maintaining cache coherency (i.e., maintaining coherency between the cache for each core and the RAM). Specifically, in the case where there are caches indicating the same data for two or more cores, if one of the cores changes that data, the data cached in the other core becomes invalid and cache misses are likely to occur. This issue is commonly known as false sharing. In the case where false sharing frequently occurs, the overhead for synchronizing the caches becomes extremely large, and therefore performance is significantly reduced compared to performance when operation with a single core processor is performed.
Technology for reducing the frequency of cache misses and executing programs efficiently by fixedly allocating a specific thread to a specific core in order to solve such issues is known (e.g. see Japanese Patent Laid-Open No. 2012-133682, para. 0075-0076, etc.).
However, in the case where a decrease in performance due to false sharing is limited to when specific processing on a specific thread is executed, if the core that operates that thread is always fixed, performance when the specific processing is not executed decreases. For example, in a case such as where performance decreases due to false sharing only while performing processing for activating a specific program in the image forming apparatus, if the operation core for the thread of that specific program remains fixed, there is a concern that performance will deteriorate when the user uses the functions of the image forming apparatus after activation, even if a reduction in performance at activation was prevented. Thus a product with performance that should have otherwise been achieved cannot be provided, and user-friendliness is impaired.